Texas Instruments OMAP5912 Reference Manual page 172

Traffic Controller
Table 41. EMIFF Low Power SDRAM Register (EMIFF_EMRS1) (Continued)
Bit Field
4:3 TCSR
2:0 PASR
Note: Bit designation is given for a 128M-bit device.
Table 42. EMIFF SDRAM Operation Register (EMIFF_OP)
Bit Field
31:25 Time-out_B3
24:18 Time-out_B2
17:11 Time-out_B1
10:4 Time-out_B0
114 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x78
Description
Temperature-compensated self-refresh
00: 70°C maximum temperature
01: 45°C maximum temperature
10: 15°C maximum temperature
11: 85°C maximum temperature
Partial-array self-refresh
000: All banks
001: 1/2 array (BA1=0)
010: 1/4 array (BA1=BA0=0)
011: Reserved
100: Reserved
101: 1/8 array (BA1=BA0=0, RA11=0)
110: 1/16 array (BA1=BA0=0, RA11=RA10=0)
111: Reserved
This register is used for SDRAM memories dedicated for low power wireless
applications. The description is given here with reference to standard devices,
but must be checked with the specification of the device actually used in a
given application.
A CPU write to this register generates a LOAD MODE register command, with
BA1=1 and BA0 = 0. Twelve bits can be loaded.
Base Address = 0xFFFE CC00, Offset = 0x80
Description
Time-out value for Bank3, in TC clock cycles.
Time-out value for Bank2.
Time-out value for Bank1.
Time-out value for Bank0.
R/W Reset
R/W 00
R/W 000
R/W Reset
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
SPRU749A