Texas Instruments OMAP5912 Reference Manual page 714

System DMA
Table 48. Global DMA Capability Register 3 (DMA_CAPS_3) (Continued)
Bit Name
1 FSC
0 ESC
Table 49. Global DMA Capability Register 4 (DMA_CAPS_4)
Bit Name
15:7 RESERVED
6 SSC
5 BIC
4 LFIC
3 FIC
2 HFIC
90 Direct Memory Access (DMA) Support
Base Address = 0xFFFE DC00, Offset = 0x58
Function
Frame synchronization capability:
0: Does not support synchronization transfer on frame
boundary.
1: Supports synchronization transfer on frame boundary.
Element synchronization capability:
0: Does not support synchronization transfer on element
boundary.
1: Supports synchronization transfer on element boundary.
Base Address = 0xFFFE DC00, Offset = 0x5A
Function
Reserved
Sync status capability:
0: Does not support synchronization transfer status bit generation.
1: Supports synchronization transfer status bit generation.
Block interrupt capability (end of block):
0: Does not support block interrupt generation capability.
1: Supports block interrupt generation capability.
Last frame interrupt capability (start of last frame):
0: Does not support last frame interrupt generation capability.
1: Supports last frame interrupt generation capability.
Frame interrupt capability (end of frame):
0: Does not support frame interrupt generation capability.
1: Supports frame interrupt generation capability.
Half frame interrupt capability (half of frame):
0: Does not support half frame interrupt generation capability.
1: Supports half frame interrupt generation capability.
R/W Reset
R 1
R 1
R/W Reset
R ND
R 1
R 1
R 1
R 1
R 1
SPRU755B