Texas Instruments OMAP5912 Reference Manual page 839

Table 8. Status Register Mapping for 512, 1024 Megabits
Bit Definition
7 7 Write protect Write protect
6 6 Device operation Device operation
5 Reserved
4 4 Plane 3 pass/fail Plane 3 pass/fail
3 Plane 2 pass/fail
2 2 Plane 1 pass/fail Plane 1 pass/fail
1 1 Plane 0 pass/fail Plane 0 pass/fail
0 0 Program/erase Program/erase
(all operations) (all operations)
2.1.8 Reset Operation
SPRU756A
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Program/erase
Read Status (70h)
0: Protected
1: Not protected
0: Busy
1: Ready
0
0 0
0
0 0
0 0
0: Pass
1: Fail
The NFMC has a reset feature executed by writing 0xFF to the command
register (NND_COMMAND_SEC) because there is no address to be sent.
When the NFMC is in a busy state during the random read program or erase
mode, the reset operation aborts these operations. The contents of memory
cells being altered are no longer valid, because the data is partially
programmed or erased and cannot be ensured. The command register of the
NFMC is cleared to wait for the next command. The R/B_ pin goes to low for
a certain time depending on the operation (typically 5, 10, or 500 µs for
Memory Interfaces for the EMIFS
0
0
0
0
0
0: Pass
1: Fail
Read Multiplane Status (71h)
0: Protected
1: Not protected
0: Busy
1: Ready
0
0: Pass
1: Fail
0: Pass
1: Fail
0: Pass
1: Fail
0: Pass
1: Fail
0: Pass
1: Fail
Memory Interfaces 33