Texas Instruments OMAP5912 Reference Manual page 170

Traffic Controller
Table 38. DLL WRD Status Register (EMIFF_DLL_WRD_STAT)
Bit Field
31:16 Reserved
15:8 CNT
7:3 Reserved
2 LOCK
1 UDF
0 OVF
Table 39. EMIFF SDRAM MRS_NEW Register (EMIFF_MRS_NEW)
Bit Field
31:10 Reserved
9 WBST
8 ResetDLL
7 Reserved
6:4 CASL
3 S/I
2:0 PGBL
Note: After the memory exits self−refresh mode, the first thing the software should do is write to the EMIFF_MRS (legacy or
new) register so that the SDRAM's mode register is set properly.
112 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x68
Description
Must be all 0.
DLL Count. Current DLL counter value for
monitoring/debug (assumes control bit ENADLL is 1
in DLL Control register.
Must be all 0.
DLL lock status (future, not in the current design)
0: DLL is not locked.
1: DLL is properly locked.
Underflow status
0: DLL is OK.
1: DLL counter underflow
Overflow status
0: DLL is OK.
1: DLL counter overflow
Base Address = 0xFFFE CC00, Offset = 0x70
Description
Must be all 0
Write burst musts be 0 (burst write same as burst
read)
This bit resets the memory device DLL when set to 1.
Must be 0
CAS idle time:
001: Reserved
010: CAS idle time = 2
011: CAS idle time = 3 (default)
Must be set to 2 for DDR
Serial = 0/Interleave=1 (must be serial)
Page burst length. Must be set to full page burst (111)
for SDRAM and burst of 8 (011) for DDR SDRAM.
R/W Reset
R 0x0000
R 0x00
R 0x00
R 0
R 0
R 0
R/W Reset
R 0x000000
R/W 0
R/W 0
R 0
R/W 011
R/W 0
R/W 111
SPRU749A