Texas Instruments OMAP5912 Reference Manual page 344

Table 34. LSB of RAM Entry Register (RAM_L_REG)
Bit Name
15:10 Ram_lsb
9:8 AP
7:0 Unused
Table 35. Global Flush Register (GFLUSH_REG)
Bit Name
31:1 Unused
0 Global_flush
Table 36. Flush One Register (FLUSH_ENTRY_REG)
Bit Name
31:1 Unused
0 Flush_entry
Table 37. MSB Read CAM Register (READ_CAM_H_REG)
Bit Name
31:3 Unused
2:0 VA_tag_l1_H
SPRU750A
Base Address = FFFE D200, Offset = 038
Function
LSB physical address
Access permission bits
Base Address = FFFE D200, Offset = 03C
Function
Flush all the nonprotected TLB entries when 1 is
written. Always 0 when read.
Warning: Flushing the whole TLB does not change the base value and the
victim counter of the lock counter register.
Base Address = FFFE D200, Offset = 040
Function
Flush the TLB entry pointed by the logical address in
CAM_H_REG and CAM_L_REG registers (even if this
entry is set protected).
Active high.
Base Address = FFFE D200, Offset = 044
Function
Table index level 1 MSB
DSP Memory Management Unit
Reset R/W
0 R/W
0 R/W
Reset R/W
0 R/W
Reset R/W
0 R/W
Reset R/W
0
DSP Subsystem
R
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