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System DMA
Example 4.
LCD Transfer: OCP_T1 (Test RAM) → LCD, Two Blocks
78
Direct Memory Access (DMA) Support
Example 4 shows a transfer from two video blocks located in memory
connected to the OCP_T1 port to the LCD controller.
The size for the LCD display is 6 x 16 pixels with 16 bits per pixels. So the length
of one video block is 6 x 16 x 2 (in bytes) + 32 bytes for the palette = 224 bytes.
If the video block 1 starts at address 0x0B0000, the bottom address of the
video block is 0x0B00DE. If the video block 2 starts at address 0x0C0000, the
bottom address of the video block is 0x0C00DE.
Step 1: Registers are set as:
DMA_LCD_CTRL
BLOCK_MODE = 1 (two blocks)
BLOCK_IT_IE = 1
BUS_ERROR_IT_IE = 1
LCD_SOURCE_PORT = 1 (IMIF)
DMA_LCD_TOP_B1_U = 0x000B
DMA_LCD_TOP_B1_L = 0x0000
DMA_LCD_BOT_B1_U = 0x000B
DMA_LCD_BOT_B1_L = 0x00DE
DMA_LCD_TOP_B2_U = 0x000C
DMA_LCD_TOP_B2_L = 0x00000
DMA_LCD_BOT_B2_U = 0x000C
DMA_LCD_BOT_B2_L = 0x00DE
Step 2: The transfer starts when the enable (hardware) signal from the
OMAP LCD controller is asserted high.
The transfer runs, and the interrupts are generated at the end of re-
spectively block 1 and 2.
DMA_LCD_CTRL [3] = block_1_it_cond = 1. This bit is a status
bit, which detects the interrupt.
When end of block 1 is reached, the DMA restarts at the top ad-
dress of block 2 and DMA_LCD_CTRL [3] is reset to be able to
detect a next interrupt.
SPRU755B
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