Texas Instruments OMAP5912 Reference Manual page 1105

SPI Master/Slave
Figure 8. DMA Receive Protocol in Master Mode With CIi = 0, CEi = 0 and CPi = 0
SCLK
Expected transition set in EDGE_CTRL 1-2 registers on GPIO [n]
PIGPIOPINSI[n]
Expected transition set in EDGE_CTRL 1-2 registers on GPIO [n]
PIGPIOPINSI [m]
PICLKOCP
GPIO_IRQSTATUSx
00...000..0000 00...100..000 00...101..000 00...001..000 0x0000
POROCPSINTERRUPTx
2-cycles deassertion
PIOCPMCMD
WR
WR
@
@
PIOCPMADDR
PIOCPMDATA[n]
1
PIOCPMDATA[m]
1
POROCPSCMDACCEPT
The software resets the interrupt status register by writing a 1 at the
corresponding bit position [n] (or [m]) after the interrupt is served.
40 Serial Interfaces SPRU760B