Texas Instruments OMAP5912 Reference Manual page 731

Multimedia processor device overview and architecture

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Table 73. DMA Logical Channel Control Register (DMA_LCH_CTRL)

Base Address = 0xFFFE D800, Offset Address = 0x2A + n*0x40

Used to control logical channel linked queue.

Defines the NEXTLCH_ID, which is used to build logical

channel chaining queue. The LOGICAL_CHANNEL_I is enabled, after the

current logical channel finishes transfer (i = 0-15).

STOP_LNK: Disables the logical channel on channel linked queue.

1: The logical channel, defined by NEXTLCH_ID, is disabled, and EN-

ABLE_LNK is disabled.

0: No logical channel in chained is disabled.

ENABLE_LNK: Defines the logical channel that is on channel linked

1: The logical channel, defined by NEXTLCH_ID, is enabled after the cur-

rent channel finishes transferring.

0: No logical channel is chained after the current logical channel.

LCH Interleave Disable

Used to control logical channel access.

LCH_Type: Defines the logical channel assignment relationship to

physical channel and associated features.

0000: LCh-2D dynamically shares PCh-0 and -1

0001: LCh-G dynamically shares PCh-0 and -1

0010: LCh-P dynamically shares PCh-0 and -1

0111: LCh-PD PCh-2

All other configurations result in undefined effects.

LCH_Interleave_Disable:

interleave mode enable.

0: Synchronized logical channel interleave mode enabled. The logical

channel transfer can be interleaved at the end of DMA request transfers.

1: A synchronized logical channel interleave mode is disabled. The logical

channel takes control of the PCh until the entire DMA data has been trans-

ferred, regardless of DMA requests. The LCh/PCh cannot be preempted

when interleaving is disabled, regardless of the LCh priority setting.

synchronized

Direct Memory Access (DMA) Support

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