Texas Instruments OMAP5912 Reference Manual page 475

Configuration
Table 30. Gate and Inhibit Control Register (GATE_INH_CTRL_0)
Bit Name
31:6 CONF_GATE_INH_
RESERVED
5 RESERVED1
4 RESERVED
3 CONF_HIGH_IMP3
2 CONF_SOFTWARE_PWR
_R
1 CONF_SOFTWARE_BVLZ
_R
0 CONF_SOFTWARE_GATE
_ENA_R
58 Initialization
Base Address = 0xFFFE 1000, Offset Address = 0x50
Function
Reserved for future expansion.
Reserved for future expansion.
Reserved for future expansion.
Controls high impedance on MCSI1.DOUT.
0: Normal function
1: Hi-Z
Controls software gating and inhibiting of the
I/O, which is gated or inhibited by COM_PWR
status.
If the gating and inhibiting logic is enabled by
FUNC_MUX_CTRL_0 (10 −13 bits) and
CONF_SOFTWARE_GATE_ENA_R is set to
1, this bit controls the com_pwr gating and
inhibiting, instead of device pins.
This bit controls software gating and inhibiting
of the I/O, which is gated or inhibited by the
BFAIL/EXT_FIQ signal.
If the gating and inhibiting logic is enabled by
FUNC_MUX_CTRL_0(10 −13)bits and
CONF_SOFTWARE_GATE_ENA_R is set to
1, this bit controls the BFAIL/EXT_FIQ gating
and inhibiting, instead of device pins.
This bit controls software gating of the I/O,
which is gated or inhibited.
If the gating and inhibiting logic is enabled by
FUNC_MUX_CTRL_0(10 −13) bits, the
software is enabled to control the gating and
inhibiting, instead of device pins.
This register controls the software gating and inhibiting functionality for the
device. The pinout section of the Application Processor Data Manual
(SPRS231) should be consulted to understand which pins are affected by the
Gated1, Gated2, Inhibit1, and Inhibit2 functions of the device.
R/W Reset
R/W 0x0000000
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
SPRU752B