Texas Instruments OMAP5912 Reference Manual page 823

1.1.2 EMIFF Configuration for OMAP1612 Stacked DDR
SPRU756A
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16Mx16 mobile DDR SRAM
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Four-bank operation
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Differential clock inputs
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MRS cycle with address key programs
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CAS latency (3)
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Burst length (2, 4, 8)
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Burst type (Sequential or Interleave)
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Partial self refresh type (1, 2, 4 banks)
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Temperature compensated self refresh
The recommended configuration sequence for using the OMAP1612 stacked
DDR is as follows. Note that Step 2 and Step 5 (refresh counter value and
delay loop) depend on the system frequency.
The refresh counter value must be calculated with the usual formula. The total
refresh time for the whole stacked DDR is 64 µs.
1) Set SDRAM_OPERATION_REG to 0x7 (high bandwidth mobile DDR
operation).
2) Set EMIFF_SDRAM_CONFIG
auto-refresh; SDRAM type = 4 banks, 256 Mbits; Refresh counter=
depends on clock frequency).
3) Set SDRAM_MANUAL_CMD_REG register to 0x7 (set CKE high
command).
4) Set SDRAM_MANUAL_CMD_REG register to 0x0 (NOP command).
5) Add a delay loop (> 500 ns).
6) Set SDRAM_MANUAL_CMD_REG register to 0x1 (PRECHARGE
command).
7) Set SDRAM_MANUAL_CMD_REG register to 0x2 (auto-refresh
command).
8) Set EMIFF_MRS_NEW register to 0x33 (burst length = 8;
CAS latency = 3).
9) Set EMIFF_EMRS1 register to 0x0 (refresh all banks; max 70_ C).
10) Set DLL_URD_CONTROL register to 0x06 (URD DLL enabled, at 90_ C).
register to 0x000xxxF6
Memory Interfaces
Introduction
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