Texas Instruments OMAP5912 Reference Manual page 385

Low-Dropout Voltage Regulator
Figure 7. LDO005 Block
VDD domain
PWRDN
Sleep
VDD
30 Clocks
POR
SETZ
LS
The reference is a circuit that delivers voltage and current to the regulator and
steady comparator. A local comparator within the reference powers up the
regulator and steadies the comparator once the reference is settled using the
PWRDN2 signal.
The voltage regulator uses an adaptive biasing technique that has a quiescent
current linearly dependent upon the load current.
The voltage comparator has an inherent dc offset. Therefore, the steady signal
is logic high when V
OUT
almost reached its steady state.
A power-on reset circuit sets the status of the LDO in power down during
ramp-up of VDD, before the status of the control inputs PWRDN and SLEEP
are in a stable state.
The sleep input signal turns the voltage regulator to power-down mode to cut
its quiescient current and turns on the PMOS switch between VDD and VOUT.
During the transition from sleep to active modes, the external capacitor holds
the voltage on VOUT to the proper level to ensure that the DPLL macros retain
the status on the internal registers for fast locking. When sleep input is low, the
PMOS switch is off.
COMP
REF
REG
PWRDN2
VDDS domain
> V to indicate that the output voltage has
OUTfinal-offset
Steady
VDDS
1.7-3.6 V
Peripheral
VOUT to DPLLs and
bond pad (1.2V − 1.6V)
SPRU751A