Internal Memory; Instruction Cache - Texas Instruments OMAP5912 Reference Manual

Figure 4. DSP Memory Connections
P bus
B bus
C bus
D bus
E bus
F bus
3.1

Internal Memory

3.2

Instruction Cache

SPRU750A
1 block of 32K bytes
PDROM
-
The DARAM (64K bytes) can support up to two memory accesses in one
CPU clock cycle into each RAM block. Accesses can be made from any
internal data, program, or DMA bus. The DARAM memory consists of
eight blocks of 8K bytes each.
-
The SARAM (96K bytes) can support one memory access in one CPU
clock cycle into each RAM block. This access can be a 32-bit value.
Accesses can be made from any internal data, program, or DMA bus. The
SARAM memory consists of 32 blocks of 8K bytes each.
-
The PDROM (32K bytes) can support one memory read in one CPU clock
cycle. This access can be a 32-bit value. Accesses can be made from any
internal data read or program bus. The PDROM memory consists of one
block of 32K bytes.
The DSP instruction cache (I-cache) module is a special-purpose, tightly
coupled, RAM-based program memory. The module is designed to
12 blocks of 8K bytes
8 blocks of 8K bytes
DARAM
SARAM
DSP Memory
To
A
external
memory
D
I/F
DSP Subsystem 23