Texas Instruments OMAP5912 Reference Manual page 380

Multimedia processor device overview and architecture

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Bypas divide

(BYPASS_DIV)

The DPLL has two modes of operation, bypass mode and lock mode.

In the bypass mode, clkout=clkref divided by 1, 2, or 4. Bypass mode

saves power because the DPLL is disabled. This mode also provides an

output clock while the DPLL circuitry is locking.

clkout = clkref

clkout = clkref/2

clkout = clkref/4

In the lock mode, the DPLL provides a synthesized output frequency that

is locked to the input reference. Lock mode is entered if the PLL_ENABLE

bit of the control register is set and the locking sequence is completed. In

this mode, the clkout contains a synthesized clock frequency as defined

clkout = PLL_MULT / (PLL_DIV+1) * clkref

clkout = 1 / (PLL_DIV + 1) * clkref for PLL_MULT = 0 or 1

Subchip control

Level shifter area

Subchip control

DPLL control

(contol register)

for BYPASS_DIV[1:0] = 00

for BYPASS_DIV[1:0] = 01

for BYPASS_DIV[1:0] = 1X

OMAP3.2 DPLL

Bypass control

for 1 < PLL_MULT <=

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