Texas Instruments OMAP5912 Reference Manual page 939

Table 23. Interrupt Register (ITR)
Bit Name Function
31:0 ACT_IRQ Sets corresponding bit in ITR for edge-sensitive and
level-sensitive interrupts.
Table 24. Mask Interrupt Register (MIR)
Bit Name
31:0 IRQ_MSK
Table 25. Interrupt Encoded Source Register for IRQ (SIR_IRQ)
Bit Name
31:5 Reserved
4:0 IRQ_NUM
Table 26. Interrupt Encoded Source Register for FIQ (SIR_FIQ)
Bit Name
31:5 Reserved
4:0 FIQ_NUM
SPRU757B
Offset: 0x00
When the MPU accesses SIR_IRQ or SIR_FIQ, the ITR bit corresponding to
the interrupt that has requested MPU action is reset. The MPU can also clear
each bit individually by writing a 0 to the corresponding bits at the ITR address.
Writing a 1 to a bit keeps its previous value. You can use the individual clearing
just before the MPU unmasks some interrupts and thus ignore some interrupt
occurrences.
Offset: 0x04
Function
Masks each incoming interrupt individually
You can mask each incoming interrupt individually with this register by setting
the corresponding bit to 1. This register operates after the interrupt register,
which means that occurrences of incoming interrupts are always stored in the
interrupt register.
Offset: 0x10
Function
Indicates encoded interrupt number that has an
IRQ request. Reading this register clears the
corresponding bit in the ITR register if the
interrupt is set as edge-sensitive.
Offset: 0x14
Function
Indicates the encoded interrupt number that has
an FIQ request. Reading this register clears the
corresponding bit in the ITR register if the
interrupt is set as edge-sensitive.
Level 1 MPU Interrupt Handler
R/W Reset
R/W 0x0000 0000
R/W Reset
R/W 0xFFFF FFFF
R/W Reset
R 00000
R/W Reset
R 00000
Interrupts 41