Texas Instruments OMAP5912 Reference Manual page 187

DPLL Modes
Synthesizing a Clock
SPRU749A
The DPLL can operate either in bypass mode or in lock mode.
-
Bypass mode
In bypass mode (PLL_ENABLE bit of the DPLL1_CTL_REG register set to
0), the DPLL output clock can be CK_REF (input reference clock),
CK_REF/2, or CK_REF/4, depending on the BYPASS_DIV bit-field value
of the DPLL1_CTL_REG register.
-
Lock mode
In lock mode (PLL_ENABLE bit of DPLL1_CTL_REG register set to 1), the
output frequency is an integer multiple or fractional multiple (m/n respec-
tively, in the PLL_MULT and PLL_DIV bit fields of DPLL1_CTL_REG reg-
ister) of the input reference clock CK_REF. With 1 ≤ m ≤ 31 and 1 ≤ n ≤ 4,
the frequency output ranges from CK_REF/4 to 31×CK_REF.
At reset, the DPLL is in bypass mode and the BYPASS_DIV bit field of the
DPLL1_CTL_REG register is set to 0b00 (DPLL output clock = CK_REF).
The procedure to synthesize a clock at a desired frequency is as follows:
1) Set the PLL_MULT and PLL_DIV bit fields of the DPLL1_CTL_REG
register to the correct value in order to get the desired multiplication factor.
2) Set the PLL_ENABLE bit to 1 to enter the lock mode.
3) When the DPLL has reached the desired synthesized clock frequency, the
bit LOCK bit of DPLL1_CTL_REG register goes to 1 and the output clock
gets the synthesized clock.
The bit fields PLL_MULT and PLL_DIV can be modified on-the-fly even when
the DPLL is in lock mode.
Polling can be done on the LOCK bit to determine when the DPLL locks on the
desired synthesized frequency. The DPLL output clock is switched smoothly
between the bypass and the locked frequency because it is not mandatory to
wait for the DPLL entering lock mode before proceeding the DPLL output
clock.
When idle mode of the DPLL is exited, the DPLL is set in bypass mode and
the output signal is valid (locked) after a maximum of 10 input reference clock
cycles. The output is valid after a maximum of 12 input reference clock cycles
Clock Generation and Reset Management
OMAP3.2 Subsystem 129