Texas Instruments OMAP5912 Reference Manual page 929

Table 10. Source FIQ Register (SIR_FIQ)
@0x14
Access
Default
Table 11. Control Register
@0x18
Access
Default
SPRU757B
This register stores the currently active IRQ interrupt number (in
hexadecimal). Reading this register clears the corresponding bit in the ITR
register if the interrupt is set as edge sensitive. Unused bits are read as 0.
In case a priority calculation is ongoing for IRQ, read to this register is stalled
until priority calculation completion.
CODE_NB_IT−1 ... 0
Active FIQ number (hexadecimal)
This register stores the currently active FIQ interrupt number (in hexadecimal).
Reading this register clears the corresponding bit in the ITR register if the
interrupt is set as edge sensitive. Unused bits are read as 0.
In case a priority calculation is ongoing for FIQ, read to this register is stalled
until priority calculation completion.
DW-1...3
Reserved
R
0
Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
R
0
2
GLOBAL_MASK NEW_FIQ_AGR
RW
0
1 0
NEW_IRQ_AGR
W W
0 0
Interrupts 31