Texas Instruments OMAP5912 Reference Manual page 143

SPRU749A
Thus, there are four important register controls:
J
ENADLL in the EMIFF_DLL_WRD_CTRL register (See Table 37)
enables or disables DLL.
J
DLLPHASE in the EMIFF_DLL_WRD_CTRL register (See Table 37)
allows a fine tuning of the delayed transaction to either 72 or 90
degrees out of phase with the internal strobe.
J
Delay in the EMIFF_DLL_WRD_CTRL register (See Table 37) is the
initial delay value of the strobe. The DLL then tries to lock in on the
correct delay. A good initial value is 0x80.
J
Write offset in the EMIFF_DLL_WRD_CTRL register (See Table 37)
is a manually generated adjustment to the DLL delay. Generally, this
field should not be used as the DLL will lock automatically with the
correct delay.
The DLLPHASE control bit is used to setup the nominal delay tracked by the
DLL. This delay can be either 72 degrees (20% of the clock period) or 90
degrees (25% of the clock period). The DLL locking range is 75/133 MHz if
configured for 90 degrees, and 66/133 MHz if configured for 72 degrees.
The maximum working frequency for the DDR interface is device-dependant.
It is limited by the speed of the traffic controller, as well as by the I/O
buffer/receiver pair used for the interface (I/O voltage, LVCMOS technology
versus SSTL2). The discussion that follows is based on a C035 device, with
the traffic controller running at the maximum speed of 96 MHz.
For mobile DDR memories, there is no low-frequency limitation, as the DLL
has been removed. The EMIF fast operational range for this type of memory
is 0/100 MHz.
The DLL can be loaded with a programmable value. The load capability can
be used either to shorten the locking time, by setting an initial value near the
expected locked state value, or to assert a given value permanently. In the
latter case, the system is said to be working in unlock mode. The unlock mode
is useful when interfacing mobile DDR at frequencies below the DLL minimum
frequency, i.e. 66 MHz if 72 degrees, or 75 MHz if 90 degrees. Obviously, the
accuracy of the delay when locked is much better, but the performance of the
unlock mode is good enough below 66 MHz.
The unlock mode is simply setup by asserting the LOADDLL bit of the DLL
control register continuously, with the delay field set to the expected value.
Traffic Controller
OMAP3.2 Subsystem 85