Texas Instruments OMAP5912 Reference Manual page 847

2.1.12 FIFO (Prefetch and Postwrite)
Table 11. Prefetch/Postwrite Mode
2.1.13 Prefetch
SPRU756A
A FIFO with prefetch and postwrite functions prevents stalling the processor
for too many cycles when reading or programming the NFMC. The host either
writes or reads this FIFO directly; the NFC state machine handles the actual
programming or reading of the NFMC.
Two bits in the NND_CTRL register of the NFC select prefetch or postwrite
mode (see Table 11).
Prefetch-Postwrite
0 – 0
0 – 1
1 – 0
1 – 1
The prefetch/postwrite can read/write in advance 1, 2, 4, 8, or 16 bytes. The
FIFO_SIZE field of the NND_FIFOCTRL register holds one of these values.
The BLOCK_COUNT field of NND_FIFOCTRL register also holds the number
of (FIFO_SIZE) chunks of data to read/write from the NFMC. An internal
counter is loaded from the NND_FIFOCTRL under certain conditions, but is
not accessible from software.
The software must assure coherence between the FIFO_SIZE and
BLOCK_COUNT values stored in the NND_FIFOCTRL.
For instance, if FIFO_SIZE equals 16, then the BLOCK_COUNT must be
programmed with 32 or 33 (if spare bytes are included).
After the host programs the read address of the page, the read command is
sent, and the host enables the prefetch bit. The internal counter is loaded with
the BLOCK_COUNT value of the NND_FIFOCTRL register. Interrupt is
asserted only if the different contributions of events (READY_EVENT,
FIFO_FULL, and so on) are not masked (see Figure 14).
The NFMC enters its busy mode as indicated by the R/B_ pin. When the NFMC
is ready, the NFC starts fetching one FIFO_SIZE byte(s) of data and begins
to fill the NFC internal FIFO. While the FIFO is being loaded with data from
NFMC, any access to data, address, and command registers is stalled.
Memory Interfaces for the EMIFS
Selected Mode
Host mode
Postwrite mode
Prefetch mode
Host mode
Memory Interfaces 41