Low Voltage With Chip Running At Reduced Clock Frequencies; Omap5912 Power Modes - Texas Instruments OMAP5912 Reference Manual

Figure 32. Release of the LOW_PWR Signal
CLK32K_IN
CK_REF
ULPD_STATE
LOW_PWR
System clock request.
Must be OMAP
wake up or a
peripheral request.
4.2

Low Voltage With Chip Running at Reduced Clock Frequencies

5

OMAP5912 Power Modes

SPRU753A
Deep sleep
If the application does not require many MIPS, operate at low voltage and
reduced frequency. For instance, at a reduced core voltage of 1.05 V, the MPU
frequency can be scaled down to 80 MHz and the traffic controller frequency
to 40 MHz.
The global OMAP5912 system power mode depends on the authorized
combinations of MPU and DSP domain states.
On OMAP5912, the power management policy (software) is run exclusively
on the MPU. The DSP domain behaves as a slave, so the DSP domain power
state transitions are performed under the control of the MPU software.
However, the transition from active to inactive for the DSP domain state is an
exception to this rule. This transition is controlled by DSP software (idle
instruction).
The power state transition of the MPU domain is controlled by software and
hardware. The hardware part is composed mainly of the ULPD module FSM,
which performs automatic transition between some of the MPU domain states.
Table 52 lists the eight possible system power modes for OMAP5912.
Awake sequence
OMAP5912 Power Modes
Awake state
Power Management 95