Texas Instruments OMAP5912 Reference Manual page 207

Table 66. MPU Restore Power Delay Register (ARM_EWUPCT)
Bit Name
31:6 RESERVED
5 REPWR_EN
4:0 EXTPWR
Table 67. Master Software Reset Register (ARM_RSTCT1)
Bit Name
31:4 RESERVED
3 SW_RST
2 DSP_RST
Note: Writing the DSP_EN bit to 0 and ARM_RST bit to 1 together initiates a global software reset.
SPRU749A
Base Address = 0xFFFE CE00, Offset = 0x0C
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Enables the external power control feature.
0: The FLASH.RP pin is set to logic low when TC is
in idle mode.
1: The FLASH.RP pin stays high when the TC idle
mode is entered.
Define the delay from FLASH.RP pin going high to
the clocks restarting. Reference clock is the EMIFS
CK_REF.
Base Address = 0xFFFE CE00, Offset = 0x10
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Global system reset. Resets both the DSP and the
MPU and peripherals. This bit is always read 0.
0: The DSP, the MPU, and the peripheral clock
domains are enabled.
1: Resets the OMAP 3.2 hardware engine. Once set
to logic 1 by the MPU processor, this bit returns to
logic 0 on the next cycles.
Resets the priority registers (TIPB module), the EMIF
configuration registers, and the MPUI control logic in
the DSP. This bit is set by the external reset pins and
is released by writing a logic 1.
0: The priority registers, the EMIF configuration
registers, and the MPUI are reset.
1: The priority registers and the EMIF configuration
registers can be programmed.
Clock Generation and Reset Management
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
0x000
1
11111
Reset
0x000
0
0
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