Texas Instruments OMAP5912 Reference Manual page 202

Clock Generation and Reset Management
Table 63. MPU Clock Control Prescaler Selection Register (ARM_CKCTL)
(Continued)
Bit Name
3:2 LCDDIV
1:0 ARM_PERDIV
For reserved bits, reading gives undefined values. Writing to has no effect.
Note:
Table 64. MPU Idle Enable Control Register 1 (ARM_IDLECT1)
Bit Name
31:13 RESERVED
12 IDL_CLKOUT_ARM This read-write bit selects the idle entry mode for the
11 RESERVED
For reserved bits, reading gives undefined values. Writing to has no effect.
Note:
144 OMAP3.2 Subsystem
Base Address = 0xFFFE CE00, Offset = 0x00
Function
Define prescaler value from the frequency of CK_GEN3 to
LCD controller clock signal
00: CK_GEN3
01: CK_GEN3/2
10: CK_GEN3/4
11: CK_GEN3/8
Define the prescaler value from the frequency of
CK_GEN1 to MPU external peripheral clock domain.
00: CK_GEN1
01: CK_GEN1/2
10: CK_GEN1/4
11: CK_GEN1/8
Base Address = 0xFFFE CE00, Offset = 0x04
Function
See note.
external DPLL output clock.
0: The clock supplied to the external DPLL output clock
remains active when the MPU enters the idle mode
(ARM_CK stopped).
1: The clock supplied to the external DPLL O/P clock is
stopped in conjunction with the MPU clock when the MPU
enters the idle mode (ARM_CK stopped).
See note.
R/W Reset
R/W 00
R/W 00
R/W Reset
R/W 0x0000
R/W 0
R/W 0
SPRU749A