Texas Instruments OMAP5912 Reference Manual page 876

Multimedia processor device overview and architecture

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Software NAND Flash Controller

Table 44. NAND Controller System Configuration Register (NND_SYSCFG)

Table 45. NAND Controller System Status Register (NND_SYSSTATUS)

Table 46. NAND Controller FIFO Test Register (NND_FIFOTEST)

Software NAND Flash Controller

Memory Interfaces

When 1, software reset sequence starts.

Controls clock activity

Bits 31-2: Reserved

Bit 1: This bit resets the NFC. This is a software reset because the resetn

pin is not used for this soft reset. By writing a 1 to this bit, the soft reset

sequence starts. This bit is automatically reset to 0 and reads always 0.

Bit 0: If set to 0, the normally enabled clock is free-running. When 1, the

module is in power-saving mode. The local or internal clock runs only

when the NFMC is accessed or an operation is ongoing.

Internal reset monitoring

Bits 31-1: Reserved

Bit 0: When 1, the NFC has finished its reset. When 0, the NFC is resetting.

When the NND_SYSTEST is used and the map bit is 1, the internal FIFO is

mapped to addressable range. It is then possible to directly read or write to the

FIFO, bypassing the NND_FIFO register. In normal mode, an access to these

registers is denied and the returned value is 0x00000000.

This section describes how to connect OMAP5912 to a NAND flash using only

the EMIFS logic (referred to throughout this chapter as the Software NAND

flash controller). The software NAND flash controller can connect to either

8-bit or 16-bit NAND flashes.

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