Texas Instruments OMAP5912 Reference Manual page 577

Table 25. Reserved Register (RESERVED_48)
Bit Name
15:0 RESERVED
Table 26. ULPD PLL Control Status Register (ULPD_PLL_CTRL_STATUS)
Bit Name
15 LOCK_STATUS
14:3 PLL_CTRL_RES
2:0 PLL_CONTROL
Table 27. Power Control Register (POWER_CTRL_REG)
Bit Name
15:13 UNUSED
12 ISOLATION_CONTROL
11 MIN_MAX_REG
10 DVS_ENABLE
9 OSC_STOP_EN
SPRU753A
Base Address = 0xFFFE 0800, Offset = 0x48
Function
Kept for software compatibility reason. Has no effect on
ULPD behavior.
Base Address = 0xFFFE 0800, Offset = 0x4C
Function
Gives the lock status of the module that
provides the high frequency clock
1: PLL locked
0: PLL unlocked
Reserved
Selects the APLL mode.
000: 19.2 MHz
010: 13 MHz
011: 12 MHz
Base Address = 0xFFFE 0800, Offset = 0x50
Function
Unused
0: Electrical isolation inactive
1: Electrical isolation active
Reset of this bit is done on powerup
reset only.@@@@
1: Operation at minimum voltage
0: Operation at nominal voltage
0: DVS feature disabled
1: DVS feature enabled
0: The oscillator is not stopped in
deep sleep mode.
1: The oscillator is stopped in deep
sleep mode.
Ultralow-Power Device
R/W Reset
R/W 0x960
R/W Reset
R Unknown
R/W 0x0
R/W 0x3
R/W Reset
R 0x0
R/W 0x0
R/W 0x1
R/W 0x0
R/W 0x1
Power Management 59