Texas Instruments OMAP5912 Reference Manual page 482

Table 35. Test Debug Control 0 Register (TEST_DBG_CTRL_0)
Bit Name
31:22 CONF_TEST_DBG_
RESERVED
21 CONF_RNG_TEST_OSC
20 CONF_RNG_SELECT_
OSC
19 CONF_DSP_BRTE_
WRITE_R
18 CONF_DSP_BRTE_
READ_R
17:8 CONF_TDBG_RESERVED
_R
7:5 CONF_TEST_DBG_
RESERVED1
4 CONF_TEST_VBUS_CELL This bit tests the UIS480 VBUS detect cell.
3 CONF_DPLL_EXT_SEL
2 CONF_VBOX_EN
1 CONF_VBOX2
0 CONF_VBOX1
SPRU752B
This 1-bit register bypasses the LDO.
Base Address = 0xFFFE 1000, Offset Address = 0x70
Function
Reserved for future expansion.
Ring oscillator divider enable.
Ring oscillator selection for characterization
Active high.
DFT WRITE signal to control DSP BRTE
memories.
DFT READ signal to control DSP BRTE
memories.
These are reserved test and debug bits for the
device. They must be set to 0 at all times to
avoid errant behavior.
Reserved for future expansion.
When set to 1, the output of the VBUS detect
logic outputs a 0.
This bit selects between the internal 48-MHz
clock generated by the APLL and an external
48-MHz clock source. When this bit is set to 1,
GPIO14 becomes the source of 48 MHz for the
device.
OMAP VBOX SW test enable. This register
must be set to 1 to enable writing to the bit
fields CONF_VBOX1 CONF_VBOX2,
CONF_DSP_BRTE_READ_R, and
CONF_DSP_BRTE_WRITE_R.
OMAP VBOX − DFT WRITE signal to control
MPU BRTE memories.
OMAP VBOX 1 − DFT READ signal to control
MPU BRTE memories.
Configuration
R/W Reset
R/W 0x0000
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x1
R/W 0x000
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x1
Initialization 65