Texas Instruments OMAP5912 Reference Manual page 1047

Dual-Mode Timer
Table 34. Timer OCP Configuration Register (TIOCP_CFG) (Continued)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x10
Bit Name
1 SOFTRESET
0 AUTOIDLE
Table 35. Timer System Status Register (TISTAT)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x14
Bit Name
31:1 RESERVED
0 RESETDONE
44 Timers
(LSB), 0x12 (MSB)
Function
Software reset. Set this bit to 1 to trigger a module
reset. The bit is automatically reset by hardware.
During reads, it always returns 0.
0: Normal mode
1: Reset the OCP and the functional domain
Interface clocks gating strategy
0: Interface clock is free-running.
1: Automatic interface gating strategy is applied,
based on the interface activity.
This register allows controlling various parameters of the OCP interface.
(LSB), 0x16 (MSB)
Function
Internal global reset monitoring:
0: Reset is ongoing
1: Reset completed
This register monitors the internal global reset status. This status bit is set to
one when all clock domains have been reset. This status can be monitored by
the software to check if the module is ready-to-use following a reset (either
hardware or software reset).
R/W Reset
R/W 0
R/W 0
R/W Reset
R 0x000 0000
R 1
SPRU759B