Data Alignment; Interrupt Generation - Texas Instruments OMAP5912 Reference Manual

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Data Alignment

During a transfer, all of the addresses computed by the DMA must be aligned

on the type of data transferred if:

Data type is s8 (8-bit scalar data); addresses can have any value.

Data type is s16 (16-bit scalar data); addresses must be aligned on 16-bit

word boundary (the lowest bit of the address is always 0).

Data type is s32 (32-bit scalar data); addresses must be aligned on 32

bit-word boundary (the 2 lowest bit of the address always 00).

When using the indexed addressing modes (element index and/or frame

index), all of the addresses computed must be aligned on the data type.

The DMA forces the address alignment by hardware on the type of data

transferred.

Each DMA channel can generate an interrupt to the processor to reflect the

transfer status. Each DMA channel has a dedicated interrupt line to the

processor. For the processor to take a DMA interrupt into account, the signals

PENINTDMA(5:0), available on the DSP boundary, must be connected to

some of the peripheral interrupt lines (PENINTPERH(20:0)).

The following interrupt sources can be programmed for every DMA channel:

End of block: The last byte of the transfer has been written to destination.

End of frame: The last byte of the current frame has been written to

destination.

Half of frame: The middle byte of the current frame has been written to

destination.

Start of last frame: The first word of the last frame has been written to

destination.

DMA request collision: A new DMA request occurred before the end of

service of the previous one.

Time-out: An access (to the source or the destination) was timed out.

To prevent a channel from definitively locking a memory or peripheral, all of the

DMA ports to memory/peripheral requests are monitored by a time-out:

When the DMA sends a request to transfer data in a channel, a time-out

counter is triggered.

When the request is acknowledged, the time-out counter is stopped.

Direct Memory Access (DMA) Support

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