Texas Instruments OMAP5912 Reference Manual page 932

Multimedia processor device overview and architecture

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Interrupt Controllers (MPU Level 2 and DSP Level 2.1)

Table 17. Status Register Bit Description

0: Reset has not occurred (functional logic is currently being reset).

1: Reset has occurred.

This bit concerns only the functional and OCP clock domains. When OCP clock domain

is being reset, OCP accesses are stalled and this bit cannot be read.

Table 18. OCP_CFG Register

DW = 32 for the MPU interrupt handler; DW = 16 for the DSP interrupt handler.

Table 19. OCP_CFG Register Bit Descriptions

Power management REQ/ACK control (see Section 2.1.5)

00: Force wake-up. An idle request is acknowledged unconditionally.

01: Reserved. Do not use.

10: Smart idle. Acknowledgement of the idle request occurs only if no incoming

interrupts are pending.

11: Reserved. Do not use.

Writing 1 to this bit generates a software reset of the module. Both OCP and functional

clock domain are reset.

This bit is write only. Reading it always returns 0. To check reset completion, use the

RESET_DONE bit in the status register.

Internal OCP clock gating strategy.

0: OCP clock is free-running.

1: Automatic OCP clock gating is applied based on OCP interface activity.

To allow for future evolution, when the software writes into this register all

reserved bits must be written as 0. These bits are currently read-only and are

always read as 0, no matter what the value written. Future evolution, however,

may have one or more of them as read/write.

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