Texas Instruments OMAP5912 Reference Manual page 1084

1.2 Interface
Table 1. SPI Interface
SPI Integration
SPIF.SCK Shift register clock
Output in master mode
Input in slave mode
SPIF.DIN Serial data Input in master mode
Serial data output in slave mode
SPIF.DOUT Serial data output in master mode
Serial data Input in slave mode
Note: this signal is always driven by OMAP5912
regardless of master or slave mode.
SPIF.CS[0] SPI chip-select 0
Configured in output in master mode
Configured in input in slave mode
SPIF.CS[3:1] External SPI chip-selects in master mode
1.3 SPI Registers
SPRU760B
Table 1 describes the SPI interface.
Start address: FFFB 0C00
Address of one register: Start address + offset address
Access supported: 16 or 32 bits
SPI uses little-endian addressing scheme.
The SPI offers input and output registers for loading data to serialize (transmit)
and reading received data (receive).
SPI Master/Slave
I/O
I/O
I/O
I/O
O
Serial Interfaces 19