Texas Instruments OMAP5912 Reference Manual page 169

Table 37. DLL WRD Control Register (EMIFF_DLL_WRD_CTRL)
Bit Field
31:26 Reserved
25:20 WO
19:16 Reserved
15:8 DLY
7:4 Reserved
3 LDLL
2 DLLP
1 ENADLL
0 RESERVED
SPRU749A
Base Address = 0xFFFE CC00, Offset = 0x64
Description
Must be all 0.
Write offset. 6-bit delay fine adjustment, signed,
range – 32...+31.
One step represents a 26.3 ps ± 10.5 ps delay
adjustment. Effective in both DLL enabled and DLL
disabled mode. Used for delaying the write clock
signal
Must be all 0.
Delay. 8-bit delay to adjust the digitally controlled
delay, to be used when the DLL is disabled.
Range 0...225
One step represents a 26.3 ps ± 10.5 ps delay
adjustment.
Must be all 0s.
Load DLL. Allows loading the delay field value into
the DLL module, as the initial value for the tracking
counter, or to force a given delay.
0: No action
1: The DLL is loaded with the delay value, if ENADLL
is 1. The DLL tracking engine is stalled.
DLLPhase. Nominal digitally controlled delay
selection. This bit has no effect if DLL is disabled
0: 72 degrees (20% of the clock period)
1: 90 degrees (25% of the clock period)
0: DLL is disabled
1: DLL is enabled.
Must be 0
Traffic Controller
R/W Reset
R
R/W
R
R/W
R
R/W
R/W
R/W
R
OMAP3.2 Subsystem
0x00
0x00
0000
0x00
0000
0
0
0
0
111