Texas Instruments OMAP5912 Reference Manual page 861

Table 19. Address Decomposition
Table 20. NAND Controller Control Register (NND_CTRL)
Bit Name
31-18 Reserved
17 PREFETCH
16 POSTWRITE
15 WRITEPROT3
14 CHIPEN3
13 WRITEPROT2
12 CHIPEN2
11 WriteProt1
10 CHIPEN1
9 WRITEPROT0
SPRU756A
This register also holds the block erase address, which must be properly
formatted before being written in this register (see Table 5). Because an
access to NND_COMMAND also sends this address to the NFMC, the
software first must write the new address in the NND_ADDR_SRC, and then
write a command through NND_COMMAND. This address remains
unchanged even if a read and a program operation are performed. Note that
the address formatting depends on whether bit A8 of NND_CTRL is set or not.
The command codes 0x00, 0x01, or 0x50 select which area of the NFMC to
access.
Size of Flash
Core (MB)
32
64
128
256
512
1024
When a page is selected, sending the command 0x00, 0x01, or 0x50
distinguishes among areas A, B, or C (spare).
Description
Reserved.
When 1, prefetch mode is enabled.
When 1, postwrite mode is enabled.
WriteProtect3. When 0, the voltage generator is reset.
ChipEnable3. When 0, NFMC device is selected.
WriteProtect2. When 0, the voltage generator is reset.
ChipEnable2. When 0, NFMC device is selected.
WriteProtect1. When 0, the voltage generator is reset.
ChipEnable1. When 0, NFMC device is selected.
WriteProtect0. When 0, the voltage generator is reset.
Memory Interfaces for the EMIFS
Block Page Address
Address in Block
A21-A13 A12-A9
A22-A13 A12-A9
A23-A14 A13-A9
A24-A14 A13-A9
A25-A14 A13-A9
A26-A14 A13-A9
Start Address
in Page
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
Memory Interfaces 55