Texas Instruments OMAP5912 Reference Manual page 234

MPU and MPUI Port
5.3 MPUI Port and MPUI Registers
Table 88. MPUI Port Registers
Name
APIRI
APIRS
Table 89. MPUI Port Interrupt Register (APIRI)
Bit Name
15:8 Reserved
7:0 MPU_IRQ [7:0]
Table 90. MPUI Port Control/Status Register (APIRS)
Bit Name
15:4 Reserved
3 ENA_WPOST_
APIRAM
176 OMAP3.2 Subsystem
This section provides information about the MPUI port and MPUI registers.
Table 88 lists the 16-bit MPUI port registers. Table 89 and Table 90 describe
the register bits.
Base Address = 0xE102 0000
Description
MPUI port interrupt
MPUI port control/status
Base Address = 0xE102 0000, Offset = 0x00
Function
Interrupt flag register for interrupts from the MPU/OCP-I
to the DSP. Active low.
Only the host can set these bits. A DSP interrupt is
generated when the MPU writes a zero to the MPU_IRQ
bits. MPU_IRQ is automatically reset by MPUI port
internal logic.
Base Address = 0xE102 0000, Offset = 0x02
Function
Enables posted write for writes to the MPUI port
RAM. Available in SAMs only.
0: Posted write disabled.
1: Posted write enabled.
R/W Offset
R/W 0x00
R/W 0x02
R/W Reset
W by 0xFF
MPU/system
DMA/OCP-I
No access
by DSP
R/W Reset
R/W by 0
MPU/system
DMA/OCP-I
No access
by DSP
SPRU749A