Texas Instruments OMAP5912 Reference Manual page 229

5.1.5 Peripheral Access
5.1.6 MPUI and DSP TIPB Bridge Time-Out
SPRU749A
In HOM, the SARAM memory requests are completely asynchronous relative
to the DSP clock. Therefore, memory accesses can be performed without
resynchronization, allowing faster communication between MPU/system
DMA/OCP-I and SARAM. Any access to DARAM or EMIF causes a bus error.
In SAM, both DSP and MPU/system DMA/OCP-I can access the entire
SARAM, DARAM, and EMIF (if API_SIZE in DSP_MPUI_CONFIG register
equals 0xFFFF, the DSP can not access the SARAM). The DARAM is located
at the byte address range from 0x000000 to 0x00FFFF in DSP memory space.
In this mode, the asynchronous host accesses from the MPUI are
resynchronized on the DSP clock internally in the MPUI port logic. In case of
conflict between MPUI and DSP accesses (MPUI and DSP attempt to access
same memory block), the DSP has the priority and the MPUI access is not
acknowledged and is delayed by one or several cycles. Nevertheless, if an
MPUI cycle begins before a DSP request, the cycle is finished before
recognizing the DSP.
In HOM, only the MPU/system DMA/OCP-I can access the DSP shared
peripherals. To determine the addresses of the peripherals. Peripherals
requests are completely asynchronous relative to DSP clocks. Therefore,
peripherals accesses can be performed without any wait states, allowing
faster communication between the MPU and peripherals. In the HOM, the
MPUI port is a simple bridge between MPU and DSP TIPB bridge for the
address, data, and control signals. The ACCESS_FACTOR bits of
(MPUI_CONTROL) control the access clock that synchronizes the transfer
between the MPUI and the MPUI port.
In SAM, both the DSP and the MPU/system DMA/OCP-I can access the DSP
peripherals. However, MPU/system DMA/OCP-I can access only the DSP
shared peripherals, and any MPUI access to DSP private peripherals causes
a time-out error.
In SAM, the asynchronous host accesses from the MPU/system DMA/OCP-I
are resynchronized internally in the DSP logic. In case of conflict between
MPUI and DSP accesses (MPUI and DSP attempt to access same peripheral),
the DSP has the priority and the MPUI waits one or several cycles.
Nevertheless, if a MPUI transfer begins before a DSP request, the access is
completed before recognizing the DSP.
When operating in HOM, an MPUI access time-out limits the maximum time
a peripheral can stall the processor. When starting an access on the DSP
MPU and MPUI Port
OMAP3.2 Subsystem 171