Texas Instruments OMAP5912 Reference Manual page 946

Registers
4.1.9 Registers
4.1.10 DSP Interrupt Interface
Table 32. DSP Interrupt Interface Registers
Name
EDGE_EN_HI
EDGE_EN_LO
48 Interrupts
6) The ISR code must be capable of doing one of the following things:
Letting the peripheral know that the interrupt generated by it has been
J
serviced so the peripheral can deassert the interrupt request
Writing to the DSP mask interrupt register (DSP_MIR) to mask the
J
level-sensitive interrupt
Here the peripheral must deassert the interrupt before the mask to the
interrupt can be removed, so that the next interrupt can be recognized.
If the peripheral deasserts the interrupt before the code in ISR tells it
to do so, then the behavior is unpredictable and the Interrupt may be
lost.
7) The DSP, when it is about to exit the ISR routine, must write a 1 to the
NEW_IRQ_AGR in the DSP_CONTROL_REG to deassert the IRQ going
to DSP and to enable a new IRQ generation.
8) The DSP exits the ISR and continues its normal code execution.
9) When the NEW_IRQ_AGR in the DSP_CONTROL_REG is written into by
DSP, the process jumps to Step 2.
This section describes the DSP interrupt interface and DSP interrupt handler
registers for the OMAP 3.2 hardware engine. DSP software configures these
registers through the DSP private TIPB. To determine the base addresses for
these registers, see the Multimedia Processor Interrupts Reference Guide
(literature number SPRU757).
Table 32 lists the DSP interface registers. Table 33 and Table 34 provide
register bit descriptions. All these registers are 16 bits wide and are controlled
directly by the DSP private TIPB.
Description
Incoming interrupt high register
Incoming interrupt low register
R/W Offset
R/W 0x00
R/W 0x02
SPRU757B