Texas Instruments OMAP5912 Reference Manual page 217

Table 76. DSP Idle Enable Control Register 2 (DSP_IDLECT2) (Continued)
Bit Name
1 EN_XORPCK
0 EN_WDTCK
Table 77. DSP Reserved Register 1 (DSP_EWUPCT)
Bit Name
15:0 RESERVED
Table 78. DSP Reserved Register 2 (DSP_RSTCT1)
Bit Name
15:0 RESERVED
SPRU749A
Base Address = 0xE100 8000 or 0x008000, Offset = 0x08
Function
Enables the external reference clock (DSPXOR_CK).
0: DSPXOR_CK clock is stopped.
1: DSPXOR_CK clock is active and can be stopped
depending on the IDLXORP_DSP bit of
DSP_IDLECT1.
Enables the internal timer/watchdog clock
(DSPWDG_CK).
0: DSPWDG_CK clock is stopped.
1: DSPWDG_CK clock is active and can be stopped
depending on the IDLWDT_DSP bit of
DSP_IDLECT1.
Base Address = 0xE100 8000 or 0x008000, Offset = 0x0C
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Base Address = 0xE100 8000 or 0x008000, Offset = 0x10
Function
Reading these bits gives undefined values. Writing to
them has no effect.
Clock Generation and Reset Management
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OMAP3.2 Subsystem
Reset
0
0
Reset
0x0
Reset
0x0
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