Texas Instruments OMAP5912 Reference Manual page 706

System DMA
Table 32. LCD Channel Register Mapping for OMAP 3.2 Respectively OMAP 3.0/3.1
Compatible Modes (Continued)
3.3 System DMA Registers
3.3.1 Summary DMA Global Registers
82 Direct Memory Access (DMA) Support
Offset Register Mapping in OMAP 3.2
Mapping Mode
E3D0 DMA_LCD_TOP_B2_L
E3D2 DMA_LCD_TOP_B2_U
E3D4 DMA_LCD_BOT_B2_L
E3D6 DMA_LCD_BOT_B2_U
E3D8 DMA_LCD_SRC_EI_B1
E3DA DMA_LCD_SRC_FI_B1_L
E3DC DMA_LCD_SRC_EI_B2
E3DE DMA_LCD_SRC_FI_B2_L
E3E0 DMA_LCD_SRC_EN_B1
E3E2 DMA_LCD_SRC_EN_B2
E3E4 DMA_LCD_SRC_FN_B1
E3E6 DMA_LCD_SRC_FN_B2
E3EA DMA_LCH_CTRL
E3F4 DMA_LCD_SRC_FI_B1_U
E3F6 DMA_LCD_SRC_FI_B2_U
All reserved bits and all reserved registers must be written to as 0x0000.
-
All reserved bits are read as 0.
-
The configuration and status registers are part of a superset that is
-
designed for a 16-bit port and a 16-bit channels DMA. This superset
enables optimal design reuse in hardware and software, and this design
reuse capability requires generic register mapping. These requirements
cause some registers to seem at times almost empty.
Table 33 lists the DMA global control registers. Table 34 through Table 50
describe the register bits. You must configure global registers before any LCh
is enabled, to avoid undefined effects.
Register Mapping in OMAP
3.0/3.1 Mapping Mode
DMA_LCD_BOT_B2_U
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SPRU755B