Texas Instruments OMAP5912 Reference Manual page 865

Table 27. Address Counter for Sending Bytes
SPRU756A
ADRCNT[1]-ADRCNT[0]
0-0
0-1
1-0
1-1
Bit 7: Reserved
Bit 8: The ChipEn0 directly controls the NFMC selection control. When
ChipEn0 is high, access to the NFMC is not allowed.When ChipEn0 goes high
during a read operation, the NFMC returns to standby mode. However, when
the NFMC is in a busy state during a program or an erase operation, the NFMC
ignores ChipEn0 and does not return to standby mode. Because software has
direct access to the ChipEn0 signal, it must be set to low when access is
performed and not set back to high before all operations to the NFMC are
terminated.
Bit 9: The WriteProt0 bit provides inadvertent write/erase protection during
power transitions. The NFMC internal high voltage generator is reset when the
WriteProt0 signal is low. This signal is low during reset and software must write
a 1 in this location before any access to the NFMC.
Bit 10: The ChipEn1 directly controls the NFMC selection control. When
ChipEn1 is high, access to the NFMC is impossible. When ChipEn1 goes high
during a read operation, the NFMC returns to standby mode. However, when
the NFMC is in a busy state during a program or an erase operation, the NFMC
ignores ChipEn1 and does not return to standby mode. Because software has
direct access to ChipEn1 signal, it must be set to low when access is
performed and not set back to high before all operations to the NFMC are
terminated.
Bit 11: The WriteProt1 bit provides inadvertent write/erase protection during
power transitions. The NFMC internal high voltage generator is reset when the
WriteProt1 signal is low. This signal is low during reset, and software must
write a 1 in this location before any access to the NFMC.
Bit 12: The ChipEn2 directly controls the NFMC selection control. When
ChipEn2 is high, access to the NFMC is impossible. When ChipEn2 goes high
during a read operation, the NFMC returns to standby mode. However, when
the NFMC is in a busy state during a program or an erase operation, the NFMC
ignores ChipEn2 and does not return to standby mode. Because software has
Memory Interfaces for the EMIFS
Number of Byte Address Sent
4 bytes sent (with least significant byte first)
3 bytes sent (with least significant byte first)
2 bytes sent (with least significant byte first)
1 byte sent (with least significant byte first)
Memory Interfaces 59