Texas Instruments OMAP5912 Reference Manual page 1115

SPI Master/Slave
Figure 13. Example of an Overflow Generation With CIi = 0, CEi = 0 and CPi = 0
MCU-DSP write
SPI_CTRL
SPEN0
1
SRCLK
SPI_SR
dNB
TSPDO
dNB
TSPDI
TSPDOEN
IRQ
RX_ndma_req
RE = 0
SPI_ISR
SPI_DSR
RX_FULL = 0
SPI_RX
Underflow Interrupt Generation
50 Serial Interfaces
1
NB+1
DATA 1
dNB
d0
dNB
d0
RE = 1
RX_FULL = 1
DATA 1
To generate an underflow interrupt, the SPI has to be in the following state:
SPI is configured in slave mode (SPI_SET2 [15] = 0).
-
Enable for underflow interrupt is active (SPI_IER [3] = 1).
-
The transmit register (SPI_TX) has not been updated between two
-
transmissions.
To release the interrupt (nIRQ) activated by the TX underflow bit (SPI_ISR [3]),
the user has to clear the Tx_underflow status bit by writing a 1 to SPI_ISR [3].
MCU-DSP write 1 in RX_overflow and RE status bits
MCU-DSP read on SPI_RX register
RD = 1; WR = 0
NB+1
d0
d0
RE = 1; RX_overflow = 1
DATA 2
RE = 0; RX_overflow = 0
RX_FULL = 0
DATA 2
SPRU760B