Texas Instruments OMAP5912 Reference Manual page 872

Multimedia processor device overview and architecture

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Memory Interfaces for the EMIFS

Table 36. NAND Controller ECC Registers (NND_ECC1...NND_ECC9) (Continued)

Table 37. NAND Controller Reset Register (NND_RESET)

RESETDMASYNCHRO

Table 38. NAND Controller FIFO Access Register (NND_FIFO)

Memory Interfaces

Holds ECC code parities accumulated on row

Holds ECC code parities accumulated on column

These registers hold the ECC code calculated while reading/writing the

NFMC. The Pxxxx{o,e (from 2048 to 8) are the parities accumulated on row,

while P4{o,e}, P2{o,e}, and P1{o,e} are the parities columns. P2048e and

P2048o are necessary only when ECC is computed on 512 bytes. For 256

bytes, those bit locations are left to 0.

Writing 1 asserts high the DMA request signal.

When 1, Reset NND_ECCx (x from 0 to 9) registers.

Bits 31-8: Reserved

Bit 7: When in host mode (no prefetch or postwrite enabled), writing a 1

in this bit asserts high the DMA request. This bit is cleared automatically.

Bits 6-1: Reserved

Bit 0: Writing a 1 in the RESET_ECC bit resets the NND_ECCx registers.

After the reset is done, RESET_ECC is reset automatically to 0. The

NND_ECCx registers are also reset when the resetn pin at the NFC

boundary goes low. After a RESET_ECC, the next ECC computation uses

the NND_ECC1 register.

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