Texas Instruments OMAP5912 Reference Manual page 925

Table 6. Interrupt Controller Registers
Register
ITR
MIR
RESERVED
RESERVED
SIR_IRQ
SIR_FIQ
CONTROL
ILR0
ILR1
ILR2
ILR3
ILR4
ILR5
ILR6
ILR7
ILR8
ILR9
SPRU757B
All unused register bits are read as 0.
The OMAP programming model ensures that no posted write occurs in any
writeable register.
Table 6 lists the interrupt controller registers. Table 7 through Table 20
describe the register bits.
Description
Interrupt register
Interrupt mask register
Reserved
Reserved
Interrupt encoded source register (IRQ)
Interrupt encoded source register (FIQ)
Interrupt control register
ILR Registers
Interrupt priority level register bit 0
Interrupt priority level register bit 1
Interrupt priority level register bit 2
Interrupt priority level register bit 3
Interrupt priority level register bit 4
Interrupt priority level register bit 5
Interrupt priority level register bit 6
Interrupt priority level register bit 7
Interrupt priority level register bit 8
Interrupt priority level register bit 9
Interrupt Controllers (MPU Level 2 and DSP Level 2.1)
R/W Offset
R/W 0x00
R/W 0x04
R 0x08
R 0x0C
R 0x10
R 0x14
R/W 0x18
R/W 0x1C
R/W 0x20
R/W 0x24
R/W 0x28
R/W 0x2C
R/W 0x30
R/W 0x34
R/W 0x38
R/W 0x3C
R/W 0x40
Interrupts 27