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Table 39. Timer Control Register (TCLR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x24
Bit
Name
31:13
RESERVED
12
PT
11:10
TRG
9:8
TCM
7
SCPWM
6
CE
5
PRE
4:2
PTV
SPRU759B
The timer wake-up enable register (TWER) allows the user to mask the
expected source of a wake-up event that generates a wake-up request. The
TWER is programmed synchronously with the interface clock before any idle
mode request coming from the host processor.
(LSB), 0x26 (MSB)
Function
Pulse or toggle mode on timer PWM output pin
0: Pulse
1: Toggle
Trigger output mode on timer PWM output pin
00: No trigger
01: Trigger on overflow
10: Trigger on overflow and match
11: Reserved
Transition capture mode on event capture input pin
00: No capture
01: Capture on low to high transition
10: Capture on high to low transition
11: Capture on both edge transition
This bit must be set or cleared while the timer is
stopped or the trigger is off.
1: Set the timer PWM output pin and select negative
pulse for pulse mode.
0: Clear the timer PWM output pin and select
positive pulse for pulse mode.
1: Compare mode is enabled.
0: Compare mode is disabled.
Prescaler enable
0: The timer clock input pin clocks the counter.
1: The divided input pin clocks the counter.
Prescale clock timer value
Dual-Mode Timer
R/W
Reset
0x00000
R
0
R/W
0x0
R/W
0x0
R/W
0
R/W
0
R/W
0
R/W
0x0
Timers
47
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