Texas Instruments OMAP5912 Reference Manual page 884

Multimedia processor device overview and architecture

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Software NAND Flash Controller

NAND Flash Device Interface Schematic

Memory Interfaces

FLASH.D[7:0] or FLASH.D[15:0]

CS: Most NAND flash devices require that CS be low during the read

access time (t

). For example, the Samsung K9K1G08U0M device

requires CS to be low during t

cannot be used for the NAND flash chip-select. To resolve this issue, a

GPIO is multiplexed on this pin so that the processor can directly control

the state of the NAND flash chip-select during accesses. However, some

NAND flash devices, such as the Samsung K9F1G08Q0M and

K9F1G16U0M, do not require that CS be low during t

of flash devices, the OMAP161X chip-select can be used directly.

R/B: During read or write operations the NAND flash device R/B signal

goes low to indicate that the device is busy and that other operations must

wait until completion. To signal the OMAP161X that the operation has

completed, the R/B signal of the NAND flash device can be connected to

Config register

Config register

FLASH.CS2UWE

FLASH.CS2UOE

. Thus, a standard OMAP161X chip-select

. For these types

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