Texas Instruments OMAP5912 Reference Manual page 1021

32-Bit Watchdog Timer General Overview
Table 11. Watchdog Load Register (WLDR)
Bit Name
31:0 TIME_LOAD
Table 12. Watchdog Trigger Register (WTGR)
Bit Name
31:0 TTGR_VALUE
Table 13. Watchdog Write Pending Register (WWPS)
Bit Name
31:5 RESERVED
4 W_PEND_WSPR
3 W_PEND_WTGR
2 W_PEND_WLDR
18 Timers
Base Address = 0xFFFE B000, Offset = 0x2C
Function
Timer counter value loaded on overflow in
autoreload mode or on WTGR write access:
32-kHz watchdog
This 32-bit register is accessible in 16-bit mode.
This register specifies the load value of the timer counter. This load value is
effective (loaded inside WCRR) after an overflow context or by triggering a
new reload via WTGR register.
Base Address = 0xFFFE B000, Offset = 0x30
Function
Trigger value. Triggers a reload of the watchdog
module by writing a value different from the
previous value inside WTGR
This 32-bit register is accessible in 16-bit mode.
A write to the watchdog trigger register (WTGR) reloads the value contained
in the WLDR register value to the watchdog counter register (WCRR).
This command is performed by writing a value inside WTGR different from the
previous value inside WTGR.
Base Address = 0xFFFE B000, Offset = 0x34
Function
Reserved
When equal to one, a write is pending to the
WSPR register.
When equal to one, a write is pending to the
WTGR register.
When equal to one, a write is pending to the
WLDR register.
R/W Reset
R/W
0xFFF0 0000
R/W Reset
R/W 0x0000 0000
R/W Reset
0x000000
R 0
R 0
R 0
SPRU759B