Texas Instruments OMAP5912 Reference Manual page 950

Registers
Table 42. Interrupt Level Register for Interrupt Number x [0−15] (DSP_ILRx)
Bit Name
15:6 Reserved
5:2 PRIORITY
1 SENS_LEVEL
0 FIQ
52 Interrupts
Offset: 0x0C
Function
Defines the priority level when the corresponding
interrupt is routed to IRQ or FIQ.
0 is the highest priority level.
15 is the lowest priority level.
0: The corresponding interrupt is rising-edge sensitive.
1: The corresponding interrupt is high-level sensitive.
0: The corresponding interrupt is routed to IRQ.
1: The corresponding interrupt is routed to FIQ.
R/W Reset
R/W 0000
R/W 0
R/W 0
SPRU757B