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Memory Interfaces for the EMIFS
Table 16. NAND Controller Revision Register (NND_REVISION)
Table 17. NAND Controller Access Register (NND_ACCESS)
Bit
Name
31-0
Data
Table 18. NAND Controller Address Register (NND_ADDR_SRC)
Bit
Name
31-0
Adress
54
Memory Interfaces
Bit
Name
31-8
Reserved
7-0
NND_REVISION
The NND_REVISION field indicates the current revision number of the NFC.
This value is fixed by hardware.
-
The 4 LSB indicate a minor revision.
-
The 4 MSB indicate a major revision.
J
0x01: Revision 0.1
J
0x02: Revision 0.2
J
0x21: Revision 2.1
Hardware reset and software reset do not act on this register.
Description
Data read/write access to external NAND flash
An access to this location performs the read or program(write) operation,
depending on the value of the MCMD signal. For program operation, data
present on the MDATA bus is written in the NFMC.
For read operation, data is fetched from the NFMC and driven on the sdata
bus. 8-bit, 16-bit, and 32-bit accesses are supported, but bytes are serialized
from/to NFC to/from NFMC. A 4 x 8-bit buffer in the NFC packs the bytes
coming from/to the NFMC.
When no operation is selected, the value 0x00000000 is driven on the SDATA
bus.
Description
External NAND flash start address
This register contains the byte address of the location in the NFMC. From this
location, the data is read or written by accessing the NAND controller access
register (NND_ACCESS). The address in this register represents the starting
address and thus is never incremented. For multiple reading and writing, the
NFMC has a pointer that is incremented.
Description
Reserved
Revision number
Reset Value
Type
0
RW
Reset Value
Type
0
RW
SPRU756A
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