Texas Instruments OMAP5912 Reference Manual page 980

2.5.1 Simultaneous Access
2.5.2 TIPB to OCP Interface
2.6 Abort Transaction
2.7 Peripheral Static Switch Configuration Registers
Table 6. Static Switch Configuration Registers Offset Addresses
Register Name
UART1_SSW_MPU_CONF
UART1_SSW_DSP_CONF
UART2_SSW_MPU_CONF
SPRU758A
Depending on the host interface protocol for the peripheral, a dedicated
wrapper is connected between the host and the peripheral bus. Two different
peripheral protocols are supported:
-
TIPB
-
OCP
Setting both the DSP
_
design. An access control and arbitration phase in the ARMPER
domain ensures that this programming conflict never occurs.
A full resynchronization process between the MPU TIPB interface, the DSP
TIPB interface, and the peripheral interface OCP clock is implemented. The
TIPB bus is stalled until the decoding of the peripheral acknowledge by the
wrapper. The decoded acknowledge is then synchronized with the TIPB
strobe to generate the ready (end of TIPB transaction).
After a predetermined number of strobe cycles (DSP_nStrobe or
MPU_nStrobe), if a peripheral did not complete the transaction, the TIPB
bridge generates an abort. The static switch uses this abort to kill the current
access. The maximum number of strobe cycles is programmable, within the
DSP TIPB bridge for DSP_nStrobe, and within the MPU TIPB bridge for
MPU_nStrobe configuration registers.
The registers listed in Table 6 are accessible through the DSP shared TIPB
bridge (16-bit access) or through the MPU shared TIPB bridge (16- or 32-bit
accesses).
# Bits
SWITCH bit and MPU
Offset
16/32 0x000
16
16/32 0x020
Peripheral Interconnects
Layer 4 Interconnect
SWITCH bits is impossible, by
_
CLK clock
_
Bus
MPU
DSP
MPU
29