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3) The frequency on the MCLK can be set accordingly: COM_RATIO_SEL[7:2]. The resulting frequency is given in
the following table:
COM_RATIO_SEL[7:2] = 0X00000, MCLK = 48 MHz
COM_RATIO_SEL[7:2] = 0X00001, MCLK = 32 MHz
COM_RATIO_SEL[7:2] = 0X00002, MCLK = 24 MHz
COM_RATIO_SEL[7:2] = 0X00003, MCLK = 19.2 MHz
COM_RATIO_SEL[7:2] = 0X00004, MCLK = 16 MHz
COM_RATIO_SEL[7:2] = 0X00005, MCLK = 13.7 MHz
COM_RATIO_SEL[7:2] = 0X00006, MCLK = 12 MHz
COM_RATIO_SEL[7:2] = 0X00007, MCLK = 9.6 MHz
COM_RATIO_SEL[7:2] = 0X00008, MCLK = 8 MHz
COM_RATIO_SEL[7:2] = 0X00009, MCLK = 6.9 MHz
COM_RATIO_SEL[7:2] = 0X000012, MCLK = 3 MHz
COM_RATIO_SEL[7:2] = 0X000032, MCLK = 1 MHz
Other programmed values in COM_RATIO_SEL[7:2] result in MCLK = 48 MHz.
4) The 48 MHz from the APLL, which can be observed on CAM.D[7], is the observability mode as configured.
5) The USB will request 48 MHz clock in case of the following event:
− The USB has detected that either an external host or an external device is attached to one of the
configured OMAP5912 USB ports, or
− The USB exits the suspend mode and enters the resume mode.
Figure 11.
Timing Diagram for Clock Request to Clock Available Latency
External clock
request
Output clock
SPRU753A
Figure 11 shows the latency between the clock request and the clock
activation.
Ti (T1, T2, T3,
T4, T5, T6, T7, T8)
The parameters (T1 to T8) are the latencies between peripheral clock requests
and clock available (see Table 5 and Table 6). These latencies depend on
ULPD setup counters and on the FSM1 state when the request is received.
Ultralow-Power Device
Power Management
39
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