Texas Instruments OMAP5912 Reference Manual page 871

Table 36. NAND Controller ECC Registers (NND_ECC1...NND_ECC9)
Bit Name
31-28 Reserved
27 P2048o
26 P1024o
25 P512o
24 P256o
23 P128o
22 P64o
21 P32o
20 P16o
19 P8o
18 P4o
17 P2o
16 P1o
15-12 Reserved
11 P2048e
10 P1024e
9 P512e
8 P256e
7 P128e
6 P64e
5 P32e
SPRU756A
Table 35. Legal Values for NND_ECC_SELECT Registers
(Continued)
NND_ECC_SELECT[2:0]
011
100
101
Any other value
Description
Reserved
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on column
Holds ECC code parities accumulated on column
Holds ECC code parities accumulated on column
Reserved
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Holds ECC code parities accumulated on row
Memory Interfaces for the EMIFS
ECC Selected
All registers above + NND_ECC6
All registers above + NND_ECC7
All registers above + NND_ECC8
All registers above + NND_ECC9
Memory Interfaces
Type Reset
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
R 0
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