Texas Instruments OMAP5912 Reference Manual page 165

Table 31. EMIFF SDRAM Configuration Register (EMIFF_CONFIG)
Bit Field
26 PWD
25:24 SDRAM
frequency
23:8 ARCV
7:4 SDRAM
type
3:2 ARE
1 Reserved
0 Slrf
SPRU749A
Base Address = 0xFFFE CC00, Offset = 0x20
Description
Power down enable. Puts the SDRAM device into power
down mode. The CKE signal to the device is held high only
for an active transaction. This bit must be enabled if the
autoclock gating is used (see SD_AUTO_CLK in the
SDRAM configuration 2 register, Table 52).
SDRAM frequency range. To control the idle time of SDRAM
regarding to the clock organization:
00: SDF0 (reset value)
01: SDF1
10: SDF2
11: SDF3
Autorefresh counter register value.
This value is calculated using the formula:
Value = (Refresh Interval/clock period/number of rows) − 50
Set the SDRAM internal organization.
Autorefresh enable. When autorefresh enable is set, the
EMIFF generates a REFR request, depending on the
autorefresh counter and the burst refresh counter. If refresh
enable is not set, the refresh must be done as a RAS_only
refresh under CPU control.
00: Autorefresh disable
01: Autorefresh enable (one command every 14.7 µs)
10: Autorefresh by burst of 4 commands
11: Autorefresh by burst of 8 commands
Must be 1
Self-refresh, when set, puts the SDRAM in self-refresh
mode if an access is made to the SDRAM after the SDRAM
automatically comes out of self-refresh.
Traffic Controller
R/W Reset
R/W
R/W
R/W 0x6188
R/W
R/W
R
R/W
OMAP3.2 Subsystem
0
00
0x0
00
1
0
107