Texas Instruments OMAP5912 Reference Manual page 184

Clock Generation and Reset Management
Figure 42. Clock Generator Module
CLKREF
4.2.1 Clock Generation Modes
Table 61. OMAP 3.2 Hardware Engine Clocking Modes
Clock Clocking Operating Mode
Select
000 Fully synchronous
001 Reserved
010 Synchronous scalable
011 Reserved
126 OMAP3.2 Subsystem
DPLL1
The clock generation and system reset module of the OMAP 3.2 hardware
engine supports four kinds of clocking modes:
-
Fully synchronous
-
Synchronous scalable
-
Bypass mode
-
Mix modes (#3 and #4)
These clocking modes provide the system with the maximum flexibility for
performance and power-saving capabilities. They are programmable by the
CLOCK_SELECT field of the (ARM_SYSST) register, and the power-up
default mode is the full synchronous mode.
Table 61 details the hardware engine different clocking modes.
MPU Clock
Source
DPLL1/N
DPLL1/M
M
CK_GEN1
u
clock generator
x
M
CK_GEN2
u
clock generator
x
M
Traffic controller
CK_GEN3
u
clock generator
x
DSP Clock
Source
DPLL1/N
DPLL1/N
CLKM1
MPU
To MPU clock
domain
CLKM2
DSP
To DSP clock
domain
CLKM3
To traffic
controller
cock domain
TC Clock Remarks
Source
DPLL1/N See Fully
Synchronous
Mode
DPLL1/O See
Synchronous
Scalable Mode
SPRU749A