Texas Instruments OMAP5912 Reference Manual page 854

Memory Interfaces for the EMIFS
Figure 17. Single-Page Read DMA in Prefetch Mode
Software programs the address.
Software programs the read command.
Software programs NND_FIFOCTRL register.
(FIFO_SIZE and BLOCK_COUNT field).
Software enables DMA in system DMA.
Software enables prefetch.
N.F.C fetches the data from the N.F.M.C and fills the
FIFO.
When FIFO is full, Fldmareqn is asserted low.
Counter is decremented.
Note: ECC not represented.
Postwrite
48 Memory Interfaces
(n) (n)
(n)
DMA reads the data from the FIFO.
When FIFO empty, triggers a prefetch, Fldmareqn is asserted.
high. When counter is 0, the prefetch is stopped.
After the host programs the address of the page to program, the program
command is sent, and the host enables the FIFO postwrite mode and DMA in
system DMA. The internal counter is loaded with the BLOCK_COUNT value
of the NND_FIFOCTRL register and the DMA request is driven low (see
Figure 18).
The DMA can write a FIFO_SIZE byte(s) in the FIFO of the NFC. When the
FIFO is full, the DMA request is asserted high and the counter is decremented
by one. The NFC sends the data to the NFMC. When all of the data is sent to
the NFMC, the FIFO is empty, and the NFC asserts low the DMA request. The
DMA can refill the FIFO. When the counter is zero, the DMA request is not
asserted any longer, and the NFC sends the data from the FIFO to the NFMC
Last prefetch as counter = 0.
(n)
(n) (n)
Ready/busy_
Fldmareqn(DMA request)
SPRU756A